Many portable electronic devices such as cameras, cellular telephones, personal digital assistants (PDAs), MP3 players, computers and other devices include an imager for capturing images. One example of an imager is a complementary metal-oxide semiconductor (“CMOS”) imager. A CMOS imager includes a focal plane array of pixels, each one of the pixels including at least one photosensor overlying a substrate for accumulating photo-generated charge in the underlying portion of the substrate. Each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to a storage region.
Each pixel has corresponding readout circuitry that includes at least a charge storage region connected to the gate of the output transistor, an output source follower transistor, a reset transistor for resetting the charge storage region to a predetermined charge level, and a row control transistor for selectively connecting the readout circuitry to a column line. The charge storage region may be constructed as a floating diffusion region. Each pixel may have independent readout circuitry, or may employ common element pixel architecture (CEPA), that may include multiple pixels sharing a single set of readout circuitry (i.e., a common reset transistor, floating diffusion region, source-follower transistor, and row-select transistor).
A pixel (including any transfer transistor) and corresponding readout circuitry is herein referred to as a “pixel circuit.” In a CMOS imager, the active elements of a pixel circuit perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel circuit for readout; and (6) output and amplification of a signal representing a reset level and pixel charge. Photo charge may be amplified when the charge moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
FIG. 1 illustrates a typical four-transistor (4T) pixel circuit 100 utilized in a pixel array of an imager, such as a CMOS imager. The pixel circuit 100 includes a pixel having a photosensor 101 (e.g., a photodiode) and a transfer transistor 103. Pixel circuit 100 also includes readout circuitry, including a storage region configured as a floating diffusion region FD, a reset transistor 104, a source follower transistor 105, and a row select transistor 106. The at least one photosensor 101 is connected to the floating diffusion region FD by the transfer transistor 103 when the transfer transistor 103 is activated by a transfer control signal TX[n]. The reset transistor 104 is connected between the floating diffusion region FD and an array pixel supply voltage VAA. A reset control signal RST[n] is used to activate the reset transistor 104, which resets the floating diffusion region FD to a known state (i.e., to a predetermined reset voltage corresponding to the array pixel supply voltage VAA), as is known in the art.
The source follower transistor 105 has its gate connected to the floating diffusion region FD and is connected between the array pixel supply voltage VAA and the row select transistor 106. The source follower transistor 105 converts the charge stored at the floating diffusion region FD into an electrical output signal. The row select transistor 106 is controllable by a row select signal RS[n] for selectively outputting the output signal VOPIX from the source follower transistor 105 onto column line 107. In a CMOS imager, two output signals are conventionally generated for each pixel circuit 100; one being a reset signal VOPIX—RST generated after the floating diffusion region FD is reset, the other being an image or photo signal VOPIX—SIG generated after charges are transferred from the photosensor 101 to the floating diffusion region FD. This process is commonly referred to as “correlated double sampling” or “CDS”. Output signals VOPIX—RST, VOPIX—SIG are selectively stored in a sample and hold circuit 1082 (FIG. 10). Once both signals have been sampled and stored, the photosensor 101 and the floating diffusion region FD are reset by activating both the transfer transistor 103 and the reset transistor 104. Integration of the photosensor 101 begins again when the transfer transistor 103 is at least partially turned off.
FIG. 2. is a schematic diagram of multiple conventional four-transistor (4T) pixel circuits 210, 220, 230 in a segment 200 of a column of a pixel array. Each pixel circuit 210, 220, 230 includes at least one pixel including a photosensor 211, 221, 231 (e.g., a photodiode) with a respective transfer transistor 213, 223, 233. Each pixel circuit 210, 220, 230 also includes respective readout circuitry, including a storage node configured as a floating diffusion region FD1, FD2, FD3, a reset transistor 214, 224, 234, a source follower transistor 215, 225, 235, and a row select transistor 216, 226, 236. The respective output voltages VOPIX[n−1], VOPIX[n], VOPIX[n+1] (which should be understood to be either the output reset voltages VOPIX—RST[n−1], VOPIX—RST[n], VOPIX—RST[n+1] or the output signal voltages VOPIX—SIG[n−1], VOPIX—SIG[n], VOPIX—SIG[n+1]) for pixel circuits 210, 220, 230 are selectively output by their respective row select transistors 216, 226, 236 onto column line 207.
Each pixel circuit 210, 220, 230 receives a reset signal (RST[n−1], RST[n], RST[n+1], respectively), a transfer signal (TX[n−1], TX[n], TX[n+1], respectively), and a row select signal (RS[n−1], RS[n], RS[n+1], respectively). While each pixel circuit 210, 220, 230 in segment 200 is shown with a single photosensor 211, 221, 231, respectively, it should be understood that pixel circuits in a pixel array may employ a common element pixel architecture (CEPA), where multiple pixels share a single set of readout circuitry (i.e., a common reset transistor, floating diffusion region, source-follower transistor, and row-select transistor).
It may be desirable to electrically connect floating diffusion regions of multiple pixel circuits (also known as “binning” the pixel circuits). For example, summation or averaging of charges generated at each pixel circuit can be used in operation of the pixel array for many purposes, such as calibration, testing, and camera settings for various exposure conditions. Such operations, however, are typically conducted in the digital domain after conversion of each output signal VOPIX from the desired set of pixel circuits. This requires significant processing resources, resulting in decreased speed of such operations and increased power usage of the pixel array. It is therefore desirable for a pixel array to provide for summation or averaging of charges in the analog domain.
Furthermore, referring back to FIG. 1, the maximum amount of charge able to be stored at the floating diffusion region FD is determinative of a conversion gain of the pixel circuit 100. The conversion gain is the ratio of output voltage VOPIX to charge stored at the floating diffusion region FD. If the floating diffusion region FD has low capacitance, meaning that a small amount of charge may be stored in the floating diffusion region FD, the conversion gain is high. A high conversion gain is preferable for low-light conditions. However, for brighter conditions, a low conversion gain is preferred. A low conversion gain may occur when the floating diffusion region FD has high capacitance and can thus store a larger amount of charge. Because the pixel circuit 100 may be used in both low and bright light situations, a variable conversion gain for the pixel circuit 100 is desirable.
It may be desirable to perform the functions described above only at select times of operating a pixel array. Additionally, it is advantageous to use identical pixel circuits in a pixel array, yet it may be desirable to bin the floating diffusion regions of only certain subsets of pixel circuits in the pixel array. Accordingly, it is desirable for a pixel array to provide for selective binning of the floating diffusion regions.
While techniques of selectively binning pixels are known in the art, these techniques require the addition of another transistor to selectively combine the floating diffusion regions. See Guidash, U.S. Published Patent Application 2006/0274176 A1. The addition of transistors to the readout circuitry architecture, however, decreases the percentage of pixel circuit area that can be devoted to the photosensor (or photosensors). This percentage is also known as the “fill factor” of the pixel circuit. A reduced fill factor adversely affects the charge capacity and dynamic range of the pixel circuit. Accordingly, it is desirable for a pixel array to provide for selective combination of the floating diffusion regions without the addition of transistors to the pixel circuit architecture.